Microprocessor based testing for core-based system on chip
Microprocessor based testing for core-based system on chip
复制标题
基于微处理器的基于内核的片上系统测试
DOI：
10.1109/dac.1999.781382
复制
发表时间：
1999
期刊：
影响因子：
--
通讯作者：
M. Nourani
中科院分区：
文献类型：
--
作者：
C. Papachristou;F. Martin;M. Nourani
本文的目的是开发一种灵活的设计测试方法，用于测试基于核心的片上系统（SOC）。该方法的新特点是使用嵌入式微处理器/存储器对测试SOC的其余组件。测试数据使用DMA技术直接下载到存储器中，而微处理器使用测试数据来测试内核。将测试结果传输至MISR进行评价。该方法具有几个重要的优势，如实现全速测试，不限制芯片的测试速度在测试过程中的测试仪的速度，并实现了很大的灵活性，因为大多数的测试过程是基于软件。一个示例系统上的实验结果进行了讨论。
The purpose of this paper is to develop a flexible design for test methodology for testing a core-based system on chip (SOC). The novel feature of the approach is the use an embedded microprocessor/memory pair to test the remaining components of the SOC. Test data is downloaded using DMA techniques directly into memory while the microprocessor uses the test data to test the core. The test results are transferred to a MISR for evaluation. The approach has several important advantages over conventional ATPG such as achieving at-speed testing, not limiting the chip speed to the tester speed during test and achieving great flexibility since most of the testing process is based on software. Experimental results on an example system are discussed.