A Survey Of Techniques for Architecting DRAM Caches
A Survey Of Techniques for Architecting DRAM Caches
复制标题
DRAM 缓存架构技术综述
DOI：
10.1109/tpds.2015.2461155
复制
发表时间：
2016
影响因子：
5.3
通讯作者：
J. Vetter
中科院分区：
文献类型：
--
作者：
Sparsh Mittal;J. Vetter
最近核心数和内存/带宽墙的增加趋势导致了芯片架构的重大改革。面对不断增长的缓存容量需求，研究人员现在已经探索了DRAM，它通常被认为是主存储器的同义词，用于设计大型最后一级缓存。然而，在主流计算系统中高效集成DRAM缓存也提出了一些挑战，并且最近提出了一些技术来解决这些挑战。在本文中，我们介绍了构建DRAM缓存的技术综述。此外，通过跨几个维度对这些技术进行分类，我们强调了它们的相似性和差异性。我们相信本文将对研究人员深入了解DRAM缓存的潜力，权衡和挑战非常有帮助。
Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture. In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. Efficient integration of DRAM caches in mainstream computing systems, however, also presents several challenges and several recent techniques have been proposed to address them. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.