A TCAM-based distributed parallel IP lookup scheme and performance analysis
A TCAM-based distributed parallel IP lookup scheme and performance analysis
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DOI：
10.1109/tnet.2006.880171
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发表时间：
2006-08
期刊：
影响因子：
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通讯作者：
K. Zheng;Chengchen Hu;Hongbin Lu;B. Liu
中科院分区：
文献类型：
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作者：
K. Zheng;Chengchen Hu;Hongbin Lu;B. Liu
使用三进制内容可寻址存储器（TCAM）进行高速IP地址查找由于其确定性的高性能而越来越受欢迎。然而，由于存储器访问速度的缓慢提高，下一代太比特路由器的路由查找引擎需要利用多个TCAM芯片之间的并行性。传统的并行方法存在冗余度大、功耗高的问题。在本文中，我们提出了一个原始的TCAM为基础的IP查找方案，实现超高的查找吞吐量和最佳的内存利用率，同时是节能的。在我们的多芯片方案中，我们设计了一个负载平衡的TCAM表构造算法，以及自适应负载平衡机制。通过减少在每个查找操作中触发的TCAM条目的数量来很好地控制功率效率。该方案使用4个133 MHz的TCAM芯片，在TCAM条目比原始路由表多25%的情况下，实现了高达533 MPPS的查找吞吐量，同时保持了ASIC实现的简单性
Using ternary content addressable memory (TCAM) for high-speed IP address lookup has been gaining popularity due to its deterministic high performance. However, restricted by the slow improvement of memory accessing speed, the route lookup engines for next-generation terabit routers demand exploiting parallelism among multiple TCAM chips. Traditional parallel methods always incur excessive redundancy and high power consumption. We propose in this paper an original TCAM-based IP lookup scheme that achieves both ultra-high lookup throughput and optimal utilization of the memory while being power-efficient. In our multi-chip scheme, we devise a load-balanced TCAM table construction algorithm together with an adaptive load balancing mechanism. The power efficiency is well controlled by decreasing the number of TCAM entries triggered in each lookup operation. Using four 133 MHz TCAM chips and given 25% more TCAM entries than the original route table, the proposed scheme achieves a lookup throughput of up to 533 MPPS while remains simple for ASIC implementation