Architecture and Circuit Design of an All-Spintronic FPGA
Architecture and Circuit Design of an All-Spintronic FPGA
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全自旋电子 FPGA 的架构和电路设计
DOI：
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发表时间：
2018
期刊：
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通讯作者：
Mingjie Lin
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作者：
Stephen M. Williams;Mingjie Lin
以FPGA为代表的可重构逻辑器件已经被公认为是尖端器件技术的驱动器。在过去的五年中，已经有了广泛的研究，利用CMOS技术结合新兴的自旋电子器件构建新型FPGA器件。不幸的是，尽管自旋电子器件技术承诺了诸如非易失性和高面积密度的理想特征，但其相对较慢的开关速度使得将它们用作CMOS晶体管的插入式替代品相当困难。因此，为了充分发挥自旋电子器件的性能优势，必须开发创新的电路和架构设计技术，为构建高性能FPGA器件而定制。在本文中，我们的目标是充分提取新的自旋为基础的器件技术的好处，通过创新的FPGA电路和架构设计技术。具体来说，我们利用称为mCell的畴壁逻辑器件的独特特性来实现到NAND-NOR逻辑的直接映射，并在这样做的过程中创建基于LUT的CMOS可重构逻辑的高吞吐量非易失性替代方案。为了实证验证我们的方法，我们进行了广泛的HSpice电路模拟。我们的仿真结果表明，对于类似的逻辑容量，与CMOS NAND-NOR FPGA设计相比，采用mCell器件的NAND-NOR FPGA设计在所有指标上都表现出色。我们不仅将平均延迟降低了约17%，而且还将不同逻辑块配置之间的路径延迟方差提高了约59%，这可以通过在配置之间具有更一致的延迟来减轻FPGA时序分析CAD工具的负担。为了判断我们的mCell FPGA在实际应用中的性能，我们将其与基于Stratix IV LUT的FPGA进行了MCNC和VTR基准测试。我们基于mCell的FPGA器件被证明与基于CMOS LUT的FPGA设计相比具有相当强的竞争力，MCNC基准测试的平均延迟和面积分别减少了约26%和64%，VTR基准测试的平均延迟和面积分别减少了13%和55%。
Reconfigurable logic device, such as FPGA, has been well-known to be the driver of cutting-edge device technology. In the last five years, there have been extensive studies on constructing novel FPGA devices using CMOS technology combined with emerging spin- tronic devices. Unfortunately, although spintronic device technol- ogy promises desirable features such as non-volatility and high area density, its relatively slow switching speed makes it quite chal- lenging to use them as drop-in replacements for CMOS transistors. As such, to fully unlock the performance benefits of spintronic de- vices, it is imperative to develop innovative design techniques of circuit and architecture that are custom-made for building high- performance FPGA devices. In this paper, we aim at fully extracting the benefits of new spin-based device technology through innovative circuit and architecture design techniques for FPGAs. Specifically, we exploit the unique characteristics of a domain-wall logic device called the mCell to achieve a direct mapping to NAND-NOR logic and in doing so create a high-throughput non-volatile alternative to LUT-based CMOS reconfigurable logic. To empirically validate our approach, we have performed extensive HSpice circuit simulations. Our simulation results have shown that, for a similar logic capacity, the NAND-NOR FPGA design with mCell devices excels across all metrics when compared to the CMOS NAND-NOR FPGA design. Not only do we reduce average delay by about 17%, but we also improve path delay variance between different logic block configurations by about 59%, which can ease the burden on the FPGA timing analysis CAD tools by having more consistent delay between configurations. To judge the performance of our mCell FPGA in practical applications, we measured it against the Stratix IV LUT-based FPGA for the MCNC and VTR benchmark suites. Our mCell-based FPGA devices prove to be quite competitive against the CMOS LUT-based FPGA design, on average reducing delay and area by approximately 26% and 64% for the MCNC benchmark, and 13% and 55% for the VTR benchmark respectively.