A Sub-10-$\mu\hbox{W}$ Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
A Sub-10-$\mu\hbox{W}$ Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
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用于 WBAN 应用的基于磁滞延迟单元拓扑的低于 10-$muhbox{W}$ 数控振荡器
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Chen
中科院分区：
文献类型：
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作者：
S. Hsu;J. Yu;Chen
本文简要介绍了一种全数字控制振荡器(DCO)的设计，该振荡器带有两个新提出的滞后延迟单元(HDC)，用于无线体域网络应用。根据电路拓扑，这两个HDC被定义为开关和级联HDC，它们提供各种传播延迟值。这些HDC形成了基于2次方延迟级DCO(P2-DCO)结构的简单振荡器结构。每个延迟级按降序提供前一个延迟级的一半延迟，从而实现低功耗和小面积特性。P2-DCO采用90 nm cmos工艺进行验证，工作频率范围宽，面积为80μm X 80μm，最低有效位分辨率为2.05 ps。在1.0V电源电压下，在3.4兆赫兹和163.2兆赫频率下测得的动态功率值分别为5.4兆和166兆赫兹(μW)。
This brief presents an all digitally controlled oscillator (DCO) design with two newly proposed hysteresis delay cells (HDCs) for wireless body area network applications. According to circuit topologies, the two HDCs are defined as on-off and cascaded HDCs that provide various propagation delay values. These HDCs form a simple oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture. Each delay stage provides half of the delay of the previous delay stage in descending order, enabling low-power and small-area features. The P2-DCO is verified in a 90-nm CMOS technology for wide operating frequencies with area of 80 μm X 80 μm and least significant bit resolution of 2.05 ps. With a supply voltage of 1.0 V, the measured dynamic power values are 5.4 and 166 μW at 3.4 and 163.2 MHz, respectively.