A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation-猫眼课题宝

DOI：

10.1007/978-3-662-53140-2_26

发表时间：

2016-08

期刊：

影响因子：

通讯作者：

中科院分区：

其他

文献类型：

作者：

Rei Ueno;S. Morioka;N. Homma;T. Aoki

本文提出了一种支持CBC模式下加解密的高效AES硬件体系结构。一些传统的AES体系结构采用流水线技术来提高吞吐量和效率。然而，这种流水线架构通常不适合，因为许多实际的加密应用程序都是在CBC模式下工作的，在这种模式下，块并行性无法用于加密。在本文中，我们提出了一种适用于这种区块链模式的高效AES加解密硬件设计。特别是，新的操作重排序和寄存器重定时技术使我们能够在没有任何延迟开销的情况下统一加密和解密（即SubBytes和InvSubBytes）的反转电路。一种新的线性映射统一技术进一步减少了区域和临界延迟。我们的设计采用了一个通用的循环架构，因此即使在CBC模式下也能有效地执行。我们还提出了一个共享的键调度数据路径，它可以在提议的体系结构中实时工作。据我们所知，所提出的体系结构具有最短的关键路径延迟，并且就每个区域的吞吐量而言，在具有塔域s盒的传统AES加密/解密体系结构中是最有效的。我们用TSMC 65纳米标准单元库和NanGate 45和15纳米开放单元库的逻辑合成结果来评估所提出的数据路径和一些传统数据路径的性能。因此，我们确认我们提出的架构比任何其他传统架构实现了大约53 - 72%的效率（即更高的bps/GE）。

This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enhance the throughput and efficiency. However, such pipelined architectures are frequently unfit because many practical cryptographic applications work in the CBC mode, where block-wise parallelism is not available for encryption. In this paper, we present an efficient AES encryption/decryption hardware design suitable for such block-chaining modes. In particular, new operation-reordering and register-retiming techniques allow us to unify the inversion circuits for encryption and decryption (i.e., SubBytes and InvSubBytes) without any delay overhead. A new unification technique for linear mappings further reduces both the area and critical delay in total. Our design employs a common loop architecture and can therefore efficiently perform even in the CBC mode. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption architectures with tower-field S-boxes. We evaluate the performance of the proposed and some conventional datapaths by logic synthesis results with the TSMC 65-nm standard-cell library and NanGate 45- and 15-nm open-cell libraries. As a result, we confirm that our proposed architecture achieves approximately 53–72 % higher efficiency (i.e., a higher bps/GE) than any other conventional counterpart.

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation

文献摘要

相似文献