Designing Application-Specific Networks on Chips with Floorplan Information-猫眼课题宝

DOI：

10.1145/1233501.1233573

发表时间：

2006-11

期刊：

2006 IEEE/ACM International Conference on Computer Aided Design

影响因子：

通讯作者：

中科院分区：

其他

文献类型：

作者：

S. Murali;P. Meloni;F. Angiolini;David Atienza Alonso;S. Carta;L. Benini;G. De Micheli;L. Raffo

随着片上系统（SoC）中处理器和存储器核的通信需求的增加，需要可扩展的片上网络（NoC）来互连核。为了在当今的工业设计中使用NoC是可行的，需要满足目标应用领域的设计目标和约束的定制的、特定于应用的NoC。在这项工作中，我们提出了一种设计方法，自动合成这种特定应用的片上网络架构。我们提出了一种布局感知的设计方法，考虑布线的复杂性的片上网络在拓扑合成过程中。这导致在设计周期早期检测NoC链路上的时序违规，并且具有互连的准确功率估计。我们将机制，以防止路由过程中的死锁，这是正确的操作的NoCs的关键。我们集成了片上网络的综合方法与现有的设计流程，自动化片上网络的综合，生成，仿真和物理设计过程。我们还提出了确保各个级别设计收敛的方法。在多个SoC基准测试平台上进行的实验表明，与最好的mesh和基于mesh的自定义拓扑结构相比，该综合拓扑结构在网络功耗方面有很大的降低（平均降低2.78倍），在性能方面有很大的提高（平均提高1.59倍）。一个实际的布局的多媒体SoC的片上网络设计使用我们的方法，这表明，所设计的片上网络支持所需的工作频率（接近900 MHz），没有任何时序违规。我们可以在4小时内设计从输入规范到布局的NoC，而这个过程通常需要几周的时间

With increasing communication demands of processor and memory cores in systems on chips (SoCs), scalable networks on chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC architectures. We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process. This leads to detecting timing violations on the NoC links early in the design cycle and to have accurate power estimations of the interconnect. We incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs. We integrate the NoC synthesis method with an existing design flow, automating NoC synthesis, generation, simulation and physical design processes. We also present ways to ensure design convergence across the levels. Experiments on several SoC benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78 times on average) and improvement in performance (1.59 times on average) over the best mesh and mesh-based custom topologies. An actual layout of a multimedia SoC with the NoC designed using our methodology is presented, which shows that the designed NoC supports the required frequency of operation (close to 900 MHz) without any timing violations. We could design the NoC from input specifications to layout in 4 hours, a process that usually takes several weeks

Designing Application-Specific Networks on Chips with Floorplan Information

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