Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing

Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
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DOI:
10.1109/ted.2018.2866048
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发表时间:
2018-10-01
影响因子:
3.1
通讯作者:
Miao, Xiang-Shui
Miao, Xiang-Shui
中科院分区:
工程技术2区
文献类型:
--
作者:
Wang, Zhuo-Rui;Li, Yi;Miao, Xiang-Shui

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内存计算体系结构是一种新兴的革命性计算范式,可以打破冯·诺伊曼的瓶颈。本文提出了一种基于CMOS1T1R阻性随机存取存储器(RRAM)集成结构的计算方法和电路协同设计。实验演示了功能完备的布尔逻辑和算术函数。采用单个40 nm工艺1T1R单元,16个二值逻辑中的每一个都可以在两个逻辑步骤中实现,并增加一个读出步骤用于级联,显示了功能重新配置和较低的计算复杂度。执行多达10(7)个NAND和XOR逻辑运算周期,以验证正确性和可靠性。此外,还设计了几种基本的加法器电路,并在1T1R器件上进行了实验验证,以验证1T1R计算体系结构的概念。本文提出的加法器包括纹波进位加法器及其优化设计和进位选择加法器,这些加法器在非易失性、计算速度和电路面积方面都显示出良好的优势。本文报道了迄今为止最复杂但最有效的基于RRAM的8位加法函数,为构建未来的内存计算体系结构奠定了坚实的基础。
In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.