Ag conductive bridge RAMs for physical unclonable functions

Ag conductive bridge RAMs for physical unclonable functions
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用于物理不可克隆功能的银导电桥 RAM

DOI:
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发表时间:
2017
期刊:
IEEE International Symposium on Hardware Oriented Security and Trust
影响因子:
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通讯作者:
M. Kozicki
M. Kozicki
中科院分区:
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文献类型:
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作者:
B. Cambou;F. Afghah;D. Sonderegger;J. Taggart;H. Barnaby;M. Kozicki

文献摘要

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我们提出了一种设计可靠的物理不可克隆功能(PUF)的方法,该方法具有基于银的导电桥随机存取存储器(CB-RAM)阵列,以保护物联网(IoT)。我们在我们的试点生产线上制造的阵列,其特点是,在极低的功率下工作,这是非常可取的安全应用,并保护密码原语。在这项工作中提出的实验数据支持选择的编程电压,Vset,作为参数,产生PUF挑战-响应对(CRP)。0.12V的中值Vset电压比其他非易失性存储器技术低几个数量级,这可以减少侧沟道分析的威胁。当与基于三元状态的方法相结合时,我们表征的Vset的单元到单元的稳定性水平是可接受的,并且导致低CRP错误率。内建自测试能力(BIST)用于区分携带状态“X”的阵列的不稳定单元与携带状态“0”和“1”的固体单元,所述固体单元能够生成可靠的PUF CRP。机器学习算法的使用还可以补偿温度漂移、噪声、老化和测量不稳定性正常变化。这项研究工作目前用于完成和设计一个原型与自定义状态机,和FPGA。我们将制作各种CB-RAM样品,以优化PUF的质量。
We are presenting a method to design reliable physical unclonable functions (PUFs), with silver based conductive-bridge random access memory (CB-RAM) arrays, to protect the internet of things (loT). The arrays that we fabricated in our pilot line, and characterized, operate at extremely low power which is highly desirable for security applications, and to protect cryptographic primitives. The experimental data presented in this work supports the selection of the programming voltage, the Vset, as the parameter, to generate PUF challenge-response pairs (CRP). The median Vset voltage at 0.12V is orders of magnitude lower than other non-volatile memory technologies, which can reduce the threat of side channel analysis. The level of stability, cell to cell, of the Vset that we characterized is acceptable when combined with methods based on ternary states, and resulted in low CRP error rates. Built-in-self-test capability (BIST) is used to differentiate unstable cells of the array, that carry the state “X”, from the solid cells carrying the states “0” and “1”, which are capable of generating reliable PUF CRPs. The use of machine learning algorithms can also compensate for the temperature drifts, noise, aging, and measurement instabilities normal variations. This research work is currently used to finalize and design a prototype with a custom state machine, and FPGA. We will fabricate various CB-RAM samples to optimize the quality of the PUFs.