Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells
Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells
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使用无时钟逻辑单元演示 8 位 SFQ 进位先行加法器
DOI：
10.1109/isec.2015.7383439
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
N. Takagi
中科院分区：
文献类型：
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作者：
T. Kawaguchi;Masamitsu Tanaka;K. Takagi;N. Takagi
我们设计、制作并实验演示了一个使用无时钟and和NIMPLY单元的8位进位前置加法器。无时钟单元是一种没有时钟输入的逻辑单元。与仅使用时钟单元的电路相比，使用无时钟单元的电路具有更少的布线线和分离器。减少导线和分路器的数量可以减小电路的面积。8位加法器核心（没有SFQ-to-DC和DC-to-SFQ转换器，时钟发生器以及用于高频测试的输入和输出移位寄存器）具有3320个约瑟夫森结（js），占用1.84 mm2的面积。其设计目标工作频率为10ghz，采用3级流水线，在2.5 mV偏置电压下，时钟输入到主输出的最大延时为74ps。加法器芯片采用AIST 10-kA/cm2先进工艺（ADP2）制造，并在低频和高频下进行测试，测量偏置裕度为+16%/+6%。测得的最大频率为12.87 GHz。
We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm2. It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm2 Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.
使用绝热量子通量参数逻辑模拟和实现 8 位进位超前加法器
DOI：
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发表时间：
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期刊：
影响因子：
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作者：
K. Inoue;N. Takeuchi;K. Ehara;Y. Yamanashi;N. Yoshikawa
通讯作者：
N. Yoshikawa