Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects
Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects
复制标题
最大电源噪声影响下的布局感知关键路径延迟测试
DOI：
10.1109/tcad.2011.2163159
复制
发表时间：
2011
影响因子：
2.9
通讯作者：
M. Tehranipoor
中科院分区：
文献类型：
--
作者：
Junxia Ma;M. Tehranipoor
随着技术的缩减，栅极对噪声的敏感度由于电源电压缩放和电压阈值的有限缩放而增加。因此，电源噪声（PSN）在100 nm以下技术中发挥着更大的作用，并造成信号完整性问题。考虑电源电压噪声影响至关重要：1）在设计验证期间，为关键路径应用足够的保护带; 2）在路径延迟测试期间，确保芯片的性能和可靠性。在本文中，提出了一种新的布局感知模式生成过程，考虑到局部电压降的影响，最大限度地提高PSN的关键路径的影响。所提出的模式生成和验证流程是在ITC'99 b19基准上实现的。引线键合和倒装芯片封装风格的实验结果。结果表明，我们提出的方法是快速的，显着增加周围的功能可测试的关键路径切换，并诱导放置在关键路径上的细胞，从而导致增加路径延迟大的电压降。所提出的方法消除了非常耗时的模式验证阶段，在工业实践中。
As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.