Data-Driven Structured Thermal Modeling for COTS Multi-core Processors
Data-Driven Structured Thermal Modeling for COTS Multi-core Processors
复制标题
DOI：
10.1109/rtss52674.2021.00028
复制
发表时间：
2021-12
期刊：
影响因子：
--
通讯作者：
Seyedmehdi Hosseinimotlagh;Daniel Enright;C. Shelton;Hyoseung Kim
中科院分区：
文献类型：
--
作者：
Seyedmehdi Hosseinimotlagh;Daniel Enright;C. Shelton;Hyoseung Kim
热感知对于部署在恶劣环境中的实时系统越来越重要。由于芯片温度过高会导致处理器内核在意外时间发生频率节流或关机，因此已经开发了许多实时调度技术，以确保安全关键任务在严格的时间约束下连续、故障安全地运行。然而，它们的实际使用在很大程度上仍然受到限制，因为如果不使用特殊的测量仪器或获取专有信息，如微建筑单元的功率轨迹和详细的平面图，获取商业处理器的精确热模型是极其困难的。本文提出了一种直接适用于实时嵌入式系统中商用现成多核处理器的数据驱动的结构化热建模方案。通过使用少量的片上温度传感器获得的温度分布，该方案可以准确地预测不同CPU频率和环境条件下动态实时工作负载下的处理器工作温度。从我们的方案得到的热模型具有快速收敛和对不同误差源的鲁棒性。我们的方案是非侵入性的，这意味着它不需要更改目标系统的软件代码或硬件包装。此外，在给定的负载和时钟频率水平下，我们的方案可以估计处理器的相对功耗。在多核ARM平台上的实验结果表明，该方案估计工作温度的最大误差为2.5%，而最新的前人工作的误差为23%。这种高度精确的建模使我们能够获得不会导致热安全违规的最大处理器利用率。
Thermal awareness is increasingly important for real-time systems deployed in harsh environments. As high chip temperature can cause frequency throttling or shutdown of processor cores at unexpected times, many real-time scheduling techniques have been developed to ensure continuous, fail-safe operation of safety-critical tasks with stringent timing constraints. However, their practical use remains largely limited due to the fact that it is extremely difficult to obtain a precise thermal model of commercial processors without using special measurement instruments or access to proprietary information, such as the power traces of micro-architectural units and detailed floorplans. In this paper, we propose a data-driven structured thermal modeling scheme that is directly applicable to commercial off-the-shelf multi-core processors used in real-time embedded systems. By using a small number of thermal profiles obtained from on-chip temperature sensors, our scheme can accurately predict the processor operating temperature under dynamic real-time workloads at various CPU frequencies and ambient conditions. The thermal model derived from our scheme is fast to converge and robust against different sources of errors. Our scheme is non-intrusive, meaning that it does not require changes to the software code or the hardware packaging of the target system. Furthermore, our scheme can estimate the relative power consumption of the processor for a given workload and clock frequency level. Experimental results from a multi-core ARM platform indicate that our scheme estimates the operating temperature with a maximum error of 2.5% while the latest prior work results in 23% error. This highly accurate modeling enables us to obtain the maximum achievable processor utilization that does not cause a thermal safety violation.