The Aladdin Approach to Accelerator Design and Modeling
The Aladdin Approach to Accelerator Design and Modeling
复制标题
阿拉丁加速器设计和建模方法
DOI：
10.1109/mm.2015.50
复制
发表时间：
2015
期刊：
影响因子：
3.6
通讯作者：
D. Brooks
中科院分区：
文献类型：
--
作者：
Y. Shao;Brandon Reagen;Gu;D. Brooks
与传统体系结构相比，用数据台和控制电路的形式进行了硬件专业化，有望具有令人印象深刻的性能和能量优势。当前的加速器研究依赖于基于RTL的合成流以产生准确的时机，功率和区域估计。这样的技术不仅需要大量的努力和专业知识，而且使用缓慢而乏味，使大型设计空间探索变得不可行。为了克服这个问题，作者开发了Aladdin，Aladdin，这是一种Pre-RTL，功能性能加速器建模框架，并展示了其在芯片上系统（SOC）模拟中的应用。阿拉丁（Aladdin）在RTL实施方面估计了0.9％，4.9％和6.6％的加速器的性能，功率和面积。 Aladdin与体系结构级的通用核心和内存层次结构模拟器集成，为研究人员提供了一种快速但准确的方法，以在SOC环境中建模加速器的功率和性能。
Hardware specialization, in the form of datapath and control circuitry customized to particular algorithms or applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerators relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but also are slow and tedious to use, making large design space exploration infeasible. To overcome this problem, the authors developed Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrated its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9, 4.9, and 6.6 percent with respect to RTL implementations. Integrated with architecture-level general-purpose core and memory hierarchy simulators, Aladdin provides researchers with a fast but accurate way to model the power and performance of accelerators in an SoC environment.