Deterministic bit-stream digital neurons
Deterministic bit-stream digital neurons
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DOI：
10.1109/tnn.2002.804284
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发表时间：
2002-11
影响因子：
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通讯作者：
David Braendler;T. Hendtlass;P. O'Donoghue
中科院分区：
文献类型：
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作者：
David Braendler;T. Hendtlass;P. O'Donoghue
在本文中，我们提出了一个确定性的比特流神经元的设计，它利用了内存丰富的细粒度现场可编程门阵列（FPGA）的架构。结果表明，确定性比特流提供了更长的随机比特流相同的精度。由于这些比特流是串行处理的，这允许实现比利用随机逻辑的神经元快得多的神经元。此外，由于细粒度FPGA的内存丰富的架构，这些神经元仍然只需要少量的逻辑来实现。这里介绍的设计已经在Virtex FPGA上实现，它允许非常规则的布局，有利于有效利用空间。这允许构建足够大的神经网络，以与商用神经网络硬件提供的速度相当的速度解决复杂任务。
In this paper, we present the design of a deterministic bit-stream neuron, which makes use of the memory rich architecture of fine-grained field-programmable gate arrays (FPGAs). It is shown that deterministic bit streams provide the same accuracy as much longer stochastic bit streams. As these bit streams are processed serially, this allows neurons to be implemented that are much faster than those that utilize stochastic logic. Furthermore, due to the memory rich architecture of fine-grained FPGAs, these neurons still require only a small amount of logic to implement. The design presented here has been implemented on a Virtex FPGA, which allows a very regular layout facilitating efficient usage of space. This allows for the construction of neural networks large enough to solve complex tasks at a speed comparable to that provided by commercially available neural-network hardware.