A global interconnect link design for many-core microprocessors
A global interconnect link design for many-core microprocessors
复制标题
多核微处理器的全局互连链路设计
DOI：
10.1145/1463768.1463787
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
Y. Ismail
中科院分区：
文献类型：
--
作者：
D. Khalil;Y. Ismail
在未来的多核微处理器中，核之间的片上全局互连链路对系统的整体性能有着重要的影响。提高吞吐量和减少这种全球链路中的巨大功耗是实现这种未来多核微处理器的关键。在深亚微米技术中，本征门延迟显著减少，导致非常短的信号转换时间，并向互连中注入高频分量。因此，电感和传输线的影响不能忽略。本文介绍了一种用于多核微处理器数据通信的全局互连链路的设计。该设计基于将互连设计和激励为低损耗的传输线，以实现在具有高数据带宽和低功耗的全局线上实现接近光速的片上传播。用所提出的设计替换在长全局互连中的传统中继器插入导致在所有方面的性能的显著改进。
In future many-core microprocessors, on-chip global interconnect links between cores have significant effects on the overall system performance. Improving the throughput and reducing the huge power dissipation in such global links is essential for enabling such future many-core microprocessors. In deep-submicron technologies, intrinsic gate delays are significantly reduced, resulting in very small signal transition times and injecting high frequency components into the interconnects. Hence, inductance and transmission line effects cannot be ignored. In this paper, the design of a global interconnect link for data communication in many-core microprocessors is presented. The presented design is based on having the interconnect designed and excited as a transmission line with low losses to enable near speed-of-light on-chip propagation on global wires with high data bandwidth and low power dissipation. Replacing the conventional repeater insertion in long global interconnects with the presented design results in significant improvements in all aspects of performance.