A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
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DOI：
10.1109/jssc.2017.2742518
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发表时间：
2017-12-01
影响因子：
5.4
通讯作者：
Cho, Thomas Byunghak
中科院分区：
文献类型：
--
作者：
Yao, Chih-Wei;Ni, Ronghua;Cho, Thomas Byunghak
提出了一种数字小数分频锁相环（PLL）。它在10 kHz至10 MHz和1 kHz至10 MHz范围内分别实现137和142 fs均方根抖动积分。当倍频比为207.0019231 [数控振荡器（DCO）频率与26 MHz参考时钟的整数倍相差50 kHz]时，以DCO频率一半运行的输出时钟可实现-78.6 dBc小数杂散。时间-数字转换器（TDC）斩波技术、通过逐次逼近寄存器模数转换器（SARADC）进行TDC精细转换以及TDC非线性校准可改善集成相位噪声和分数杂散。该设计满足5 GHz ISM频段256-QAM 4 x 4 MIMO LTE标准以及28 GHz频段5G蜂窝64-QAM标准的性能要求。这项工作，在14纳米鳍形场效应晶体管（FinFET）CMOS工艺实现，集成到蜂窝RF集成电路，支持先进的载波聚合操作。该PLL的功耗为13.4 mW，占用空间为0.257 mm（2）。
A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a -78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM 4 x 4 MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm(2).