Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
复制标题
可通过 Verilog 到路由 CAD 流程定位的可综合标准单元 FPGA 结构
DOI：
10.1145/3024063
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
J. Anderson
中科院分区：
文献类型：
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作者：
Jin Hee Kim;J. Anderson
在这篇文章中，我们考虑使用标准单元设计方法实现现场可编程门阵列（FPGA），并提出了一个自动生成可合成FPGA结构的框架。开源Verilog-to-Routing（VTR）FPGA架构评估框架[Rose et al. 2012]经过扩展，为其内存中的FPGA架构设备模型生成可合成的Verilog。Verilog随后可以被合成为标准单元，使用ASIC设计流程放置和布线。VTR的第二扩展为FPGA生成配置比特流，其中比特流配置FPGA以实现用户提供的布局和布线设计。所提出的框架和方法使硅实现广泛的VTR建模的FPGA结构。在一项实验研究中，面积和时序优化的FPGA实现在65纳米台积电标准单元相比，65纳米Altera商业FPGA。此外，我们考虑增加通用标准单元库从台积电与手动设计和布局的FPGA特定的细胞。我们证明了实用的定制单元在减少合成的FPGA织物的面积。
In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.