A ReRAM Memory Compiler with Layout-Precise Performance Evaluation
A ReRAM Memory Compiler with Layout-Precise Performance Evaluation
复制标题
具有布局精确性能评估功能的 ReRAM 内存编译器
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Edward Lee;D. Kim;Venkata Chaitanya Krishna Chekuri;Yun Long;S. Mukhopadhyay
本文首次提出了一种设计自动化方法，用于生成基于1T-1R的电阻随机存取存储器（ReRAM）阵列，并对其布局进行精确的性能评估。在此基础上开发并演示了一个ReRAM内存编译器，该编译器能够解释致力于提高ReRAM设备性能的独特外围电路。给定目标规格（例如内存容量，工作频率），编译器生成ReRAM子阵列并构建具有性能/功率模型的面积/功率优化阵列，用于评估和设计空间探索（DSE）。该工具使用ReRAM器件模型和65nm CMOS技术进行了演示。
This paper presents, for the first time, a design automation methodology to generate 1T-1R based Resistive Random Access Memory (ReRAM) arrays with layout-precise performance evaluation. A ReRAM memory compiler is developed and demonstrated on this basis with the ability to account for the unique peripheral circuits devoted to improving performance of ReRAM devices. Given target specifications (e.g. memory capacity, operating frequency), the compiler generates ReRAM sub-arrays and constructs area/power-optimized arrays with performance/power models for evaluation and design space exploration (DSE). The tool is demonstrated with ReRAM device models and 65nm CMOS technology.