Low Power BIST for Scan-Shift and Capture Power
Low Power BIST for Scan-Shift and Capture Power
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DOI：
10.1109/ats.2012.27
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发表时间：
2012-11
期刊：
影响因子：
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通讯作者：
Yasuo Sato;Senling Wang;Takaaki Kato;K. Miyase;S. Kajihara
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文献类型：
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作者：
Yasuo Sato;Senling Wang;Takaaki Kato;K. Miyase;S. Kajihara
为了实现准确、高效的测试，低功耗测试技术得到了深入的研究。虽然有很多成熟的扫描测试方法被提出，但由于逻辑BIST的随机性不可控，因此还没有太多成熟的方法。然而，逻辑BIST目前成为系统调试或现场测试的关键。本文提出了一种新的低功耗BIST技术，通过消除特定的高频部分的矢量，降低了移位功率，也降低了捕获功率。结果表明，该技术不仅降低了测试功耗，而且在保持测试覆盖率的同时损失很小。
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that reduces shift-power by eliminating the specified high-frequency parts of vectors and also reduces capture power. The authors show that the proposed technology not only reduces test power but also keeps test coverage with little loss.