Multibeam Digital Array Receiver Using a 16-Point Multiplierless DFT Approximation

Multibeam Digital Array Receiver Using a 16-Point Multiplierless DFT Approximation
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DOI:
10.1109/tap.2018.2882629
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发表时间:
2019-02
影响因子:
5.7
通讯作者:
V. Ariyarathna;D. Coelho;S. Pulipati;R. Cintra;F. M. Bayer;V. Dimitrov;A. Madanayake
V. Ariyarathna;D. Coelho;S. Pulipati;R. Cintra;F. M. Bayer;V. Dimitrov;A. Madanayake
中科院分区:
计算机科学2区
文献类型:
--
作者:
V. Ariyarathna;D. Coelho;S. Pulipati;R. Cintra;F. M. Bayer;V. Dimitrov;A. Madanayake

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一个 $N$ 元素阵列,其接收器经过 $N$ 点空间快速傅立叶变换 (FFT),产生 $N$ 定向正交射频 (RF) 波束。 FFT 是一种快速算法,用于以降低的复杂性计算 N$ 点离散傅立叶变换 (DFT)。 DFT 的强力计算需要 $\mathcal {O}(N^{2})$ 乘法,而 FFT 在 $\mathcal {O}(N \log N)$ 乘法下提供相同的计算。 DFT 计算的数字芯片面积和功耗仍然由所使用的 FFT 所需的乘法器决定。本文提出了一种 16 点 DFT 的近似方法,它保持接近理想 16 点 DFT 的数学特性,通过在数字实现中以显着较低的面积和功耗在每个时钟周期计算近似空间 DFT 来获得 16 个 RF 波束。所提出的近似可以使用无乘法器的类似 FFT 的快速算法来实现,从而进一步将与传统 FFT 方法中的乘法相关的数字芯片面积和功耗减少到零。 16 波束波束形成器采用 16 元件线性贴片天线阵列、直接转换接收器和时钟频率为 240 MHz 的基于 Xilinx Virtex-6 现场可编程门阵列的实时数字后端,作为 16 个复值 (IQ) 接收模式 RF 波束的实现示例,中心频率为 2.4 GHz,每个波束带宽为 120 MHz。
An $N$ -element array with receivers subject to an $N$ -point spatial fast Fourier transform (FFT) leads to $N$ directionally orthogonal radio frequency (RF) beams. FFTs are fast algorithms for computing the $N$ -point discrete Fourier transform (DFT) at reduced complexity. The brute-force computation of a DFT requires $\mathcal {O}(N^{2})$ multiplications while an FFT provides the same computation at $\mathcal {O}(N \log N)$ multiplications. The digital chip area and power consumption of the DFT computation are still dominated by the multipliers required by the FFT used. In this paper, an approximation to the 16-point DFT is proposed which maintains mathematical properties close to the ideal 16-point DFT to obtain 16 RF beams by computing an approximate spatial DFT in every clock cycle at significantly lower area and power in the digital realization. The proposed approximation can be implemented using FFT-like fast algorithms that are multiplierless, thereby further reducing the digital chip area and power consumption associated with multiplication in a conventional FFT approach to zero. A 16-beam beamformer employing a 16-element linear array of patch antennas, direct-conversion receivers, and a Xilinx Virtex-6 field-programmable gate array-based real-time digital back-end clocked at 240 MHz are described as an example realization of 16 complex-valued (IQ) receive-mode RF beams, centered at 2.4 GHz with 120 MHz of bandwidth per beam.