A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
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DOI：
10.1109/jssc.2010.2089657
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发表时间：
2011-01-01
影响因子：
5.4
通讯作者：
De, Vivek K.
中科院分区：
文献类型：
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作者：
Bowman, Keith A.;Tschanz, James W.;De, Vivek K.
45 nm微处理器内核集成了弹性错误检测和恢复电路，以缓解动态参数变化的时钟频率（F-CLK）保护带，从而提高吞吐量和能效。内核支持两种不同的错误检测设计，允许直接比较相对的权衡。第一种设计在关键路径中嵌入错误检测时序（EDS）电路，以检测延迟时序转换。除了减少动态变化的F-CLK保护带之外，嵌入式EDS设计还可以利用路径激活率，使微处理器的运行速度比不经常激活的关键路径更快。第二种错误检测设计通过在每个流水线级放置一个可调副本电路（TRC）来监控最坏情况下的延迟，从而提供了一种侵入性较低的动态时序错误检测方法。尽管TRC需要延迟保护带来确保TRC延迟始终慢于关键路径延迟，但TRC设计以较少的实现开销获得了嵌入式EDS设计的大部分优势。此外，虽然内核最小延迟约束限制了嵌入式EDS设计的潜在优势，但TRC设计的一个显著优势是能够检测更宽范围的动态延迟变化，如通过低电源电压（V-CC）测量所证明的。这两种错误检测设计都与错误恢复技术相结合，能够检测和纠正快速变化的变化（如高频V-CC下降）中的时序错误。微处理器内核还支持两种独立的错误恢复技术，以确保即使动态变化持续存在也能正确执行。第一种技术要求时钟控制以1/2F（CLK）重放错误指令。相比之下，第二种技术是一种新的多发布指令重放设计，它以较低的性能损失纠正错误指令，并且不需要时钟控制。硅测量表明，弹性电路能够在相同的能量下实现41%的吞吐量增益，或者在相同的吞吐量下实现22%的能量减少，与传统设计相比，当执行具有10% V-CC下垂的基准程序时。此外，该微处理器还包括一个新的自适应时钟控制电路，该电路与弹性电路和锁相环（PLL）接口，以跟踪恢复周期，并通过动态改变F-CLK来适应持续错误，以实现最大效率。
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F-CLK) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the F-CLK guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (V-CC) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency V-CC droops.The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2F(CLK). In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% V-CC droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing F-CLK for maximum efficiency.