High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors
High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors
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通过使用寄生晶体管的无矢量测试技术实现电路内 IC 引脚故障的高故障覆盖率
DOI：
10.1109/test.1996.557156
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
Jack Ferguson
中科院分区：
文献类型：
--
作者：
Jack Ferguson
开发了一种无矢量测试技术，该技术使用简单的晶体管测试来检测和隔离所有类型的IC上与I/O相关的故障，从简单的器件到复杂的ASIC，其优点是无需使用功能测试作为备份即可提供高故障覆盖率。寄生晶体管测试(PTT)技术利用了存在于所有类型单片IC的X/O引脚之间的固有双极晶体管效应。测试不需要向电路板通电，也不需要像在线功能测试技术通常所要求的那样反向驱动IC。编程工作量很小，因为不需要对IC建模或知道它们的功能。为了测试IC，执行简单的三针晶体管测试，然后在器件周围重复测试，直到器件上的所有管脚都在至少一次三针测试中使用。通过适当偏置每次测试中使用的管脚，可以产生并测量有源晶体管电流，以确定这三个管脚连接的完整性。
A vectorless test technique has been developed that uses a simple transistor test to detect and isolate I/O related faults on all types of ICs, from simple devices to complex ASICs, that has the advantage of providing high fault coverage without using function test as a back-up. The parasitic transistor test (PTT) technique makes use of the inherent bipolar transistor effect that exists between X/O pins on all types of monolithic ICs. Tests are performed without applying power to the board and without the need to backdrive ICs, as is normally required for in-circuit functional test techniques. Programming effort is minimal, since it is not necessary to model the ICs or know their functionality. To test an IC, a simple three pin transistor test is performed and then repeated around the device until all pins on the device have been used in at least one three-pin test. By properly biasing the pins used in each test, an active transistor current can be generated and measured to determine the integrity of the connection of those three pins.