A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction
A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction
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基于具有协同调节和降低 IR 压降的模拟辅助数字 LDO 的分布式供电网络
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
P. Mok
中科院分区：
文献类型：
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作者：
Yasu Lu;Fan Yang;Feng Chen;P. Mok
本文介绍了一种基于模拟辅助数字LDO（AADLDO）的片上分布式电源传输网格（DPDG），它继承了模拟控制的低输出涟漪和亚LSB电流供应能力的优点，以及数字控制的低电源电压工作和自适应快速响应的优点。采用分布式电源传输拓扑，可以降低电源轨上的IR压降，尤其是在大面积电源应用中。电力输送网格中的AADLDO协同工作以获得改进的响应速度与电力消耗之间的平衡。采用65 nm CMOS工艺制造了一个3 × 3电源网格原型，该原型具有9个AADLDO，提供了500 mA的最大负载电流，片内0.9 nF输出电容，以证明所提出的DPDG概念和该方案的有效性。在450 mA/20 ns的负载阶跃下，最大电压下冲为125 mV，品质因数低至0.249ps。
This paper introduces an on-chip distributed power delivery grid (DPDG) with cooperative regulation and IR-drop reduction based on analog-assisted digital LDOs (AADLDOs), which inherit the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control. With the distributed power delivery topology, the IR-drop across the power supply rail can be reduced, especially in large area power-supply applications. The AADLDOs in the power delivery grid work cooperatively to obtain a balance between improved response speed and power consumption. A prototype of a 3 × 3 power grid with 9 AADLDOs, providing a total of 500-mA maximum load current with an on-chip 0.9-nF output capacitor, is fabricated in a 65-nm CMOS process to demonstrate the proposed DPDG concept and the effectiveness of this scheme. A maximum voltage undershoot of 125mV is measured with a 450mA/20ns load step, resulting a figure-of-merit as low as 0.249ps.