A hardware framework for on-chip FPGA acceleration
A hardware framework for on-chip FPGA acceleration
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片上FPGA加速的硬件框架
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
M. Re
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文献类型：
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作者：
A. Lomuscio;G. Cardarilli;A. Nannarelli;M. Re
本文提出了一种在可重构平台上动态加载硬件加速器的新框架。在提供专用处理器库的情况下，我们将特定的处理器动态加载到FPGA中，并将执行从CPU转移到基于FPGA的加速器。结果表明，在处理器旁边放置可重构结构的片上系统上，所提出的加速框架可以获得显著的加速效果。这种加速既是由于特定于应用程序的处理器的内在加速，也是因为增加了并行度。
In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.