Low-capture-power test generation for scan-based at-speed testing
Low-capture-power test generation for scan-based at-speed testing
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DOI：
10.1109/test.2005.1584068
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发表时间：
2005-11
期刊：
影响因子：
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通讯作者：
X. Wen;Yoshiyuki Yamashita;Shohei Morishima;S. Kajihara;Laung-Terng Wang;K. Saluja;K. Kinoshita
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文献类型：
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作者：
X. Wen;Yoshiyuki Yamashita;Shohei Morishima;S. Kajihara;Laung-Terng Wang;K. Saluja;K. Kinoshita
基于扫描的全速测试是深亚微米时代保证时序相关测试质量的关键技术。然而，它的适用性受到严重挑战，因为显着的产量损失可能会发生从电路故障，由于过度的IR下降引起的高功耗时，测试响应被捕获。本文提出了一种新的低捕获功耗的X填充方法来解决这个关键问题，该方法将0和1分配给ATPG过程中获得的测试立方体中的未指定（X）位。该方法减少了捕获模式下的电路切换活动，并且可以很容易地并入任何测试生成流程中，以实现捕获功率降低，而不会对面积、时序或故障覆盖率产生任何影响。该方法生成的测试向量降低了测试良率损失的风险，极大地提高了基于扫描的全速测试的适用性
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0's and 1's to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss