On-chip training of memristor crossbar based multi-layer neural networks
On-chip training of memristor crossbar based multi-layer neural networks
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DOI：
10.1016/j.mejo.2017.05.005
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发表时间：
2017-08-01
影响因子：
2.2
通讯作者：
Yakopcic, Chris
中科院分区：
文献类型：
--
作者：
Hasan, Raqibul;Taha, Tarek M.;Yakopcic, Chris
忆阻器交叉阵列在模拟域中并行执行乘加运算，因此可以使神经形态系统在低能量和面积消耗下具有高吞吐量。这些系统的片上训练具有能够绕过器件可变性和故障的显著优势。本文提出了一种多层神经网络的片上训练电路，每层使用一个交叉开关，每个突触使用两个忆阻器。与每个突触仅使用一个忆阻器的设计相比，每个突触使用两个忆阻器提供了双倍的突触权重精度。所提出的片上训练系统利用反向传播（BP）算法进行突触权重更新。由于每个突触使用两个忆阻器，我们利用一种新的技术进行误差反向传播。我们评估了一些非线性可分离的数据集，通过详细的SPICE模拟，其中考虑到交叉线电阻和潜行路径的系统的训练。我们的研究结果表明，在所提出的设计中，交叉开关消耗的功率比每个突触设计的单个忆阻器少约9倍。
Memristor crossbar arrays carry out multiply-add operations in parallel in the analog domain, and so can enable neuromorphic systems with high throughput at low energy and area consumption. On-chip training of these systems have the significant advantage of being able to get around device variability and faults. This paper presents on-chip training circuits for multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed on-chip training system utilizes the back propagation (BP) algorithm for synaptic weight update. Due to the use of two memristors per synapse, we utilize a novel technique for error back propagation. We evaluated the training of the system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. Our results show that in the proposed design, the crossbars consume about 9x less power than single memristor per synapse design.