Accuracy-guaranteed bit-width optimization
Accuracy-guaranteed bit-width optimization
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DOI：
10.1109/tcad.2006.873887
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发表时间：
2006-10-01
影响因子：
2.9
通讯作者：
Constantinides, George A.
中科院分区：
文献类型：
--
作者：
Lee, Dong-U.;Gaffar, Altaf Abdul;Constantinides, George A.
提出了一种自动静态方法，用于优化定点前馈设计的位宽度并保证精度，称为 MiniBit。描述了最小化定点信号的整数部分和小数部分以最小化电路面积的方法。对于范围分析，本文中的技术确定了满足范围要求所需的整数位数。对于精度分析，采用具有分析误差模型的半分析方法与自适应模拟退火相结合来优化分数位数。分析模型可以保证用户指定的输入间隔内所有输入的上溢/下溢保护和数值准确性。使用现场可编程门阵列 (FPGA) 的流编译器，通过在 Xilinx Virtex-4 FPGA 上放置和路由的多项式近似、RGB 到 YCbCr 转换、矩阵乘法、B 样条和离散余弦变换来演示本文的方法。与使用最佳统一分数位宽度的设计相比，给定设计的改进可将面积和延迟分别减少多达 26% 和 12%。研究表明，MiniBit 优化设计的面积与整数线性规划方法产生的面积相差不到 1%。
An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented. Methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing the circuit area,are described. For range analysis, the technique in this paper identifies the number of integer bits necessary to meet range requirements. For precision analysis, a semianalytical approach with analytical error models in conjunction with adaptive simulated annealing is employed to optimize the number of fraction bits. The analytical models make it possible to guarantee overflow/underflow protection and numerical accuracy for all inputs over the user-specified input intervals. Using a stream compiler for field-programmable gate arrays (FPGAs), the approach in this paper is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA. Improvements for a given design reduce the area and the latency by up to 26% and 12%, respectively, over a design using optimum uniform fraction bit widths. Studies show that MiniBit-optimized designs are within 1% of the area produced from the integer linear programming approach.