Low- voltage folded-switching mixers in 0.18 μm CMOS
Low- voltage folded-switching mixers in 0.18 μm CMOS
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DOI：
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发表时间：
2005
影响因子：
5.4
通讯作者：
V. Vidojkovic;van der Jd Johan Tang;A. Leeuwenburgh;Van Roermund
中科院分区：
文献类型：
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作者：
V. Vidojkovic;van der Jd Johan Tang;A. Leeuwenburgh;Van Roermund
CMOS技术的缩放对模拟设计有很大的影响。最严重的后果是电压供应的减少。本文提出了一种低电压、低功率、电流复用的交流耦合折叠开关混频器。所介绍的混频器拓扑结构的主要优点是：高电压增益、中等噪声系数、中等线性度和在低电源电压下工作。通过分析电压增益、噪声系数（NF）、线性度（IIP3）和直流稳定性，深入了解混频器的运行情况。该混频器采用0.18µm CMOS技术设计和实现，可选择金属-绝缘体-金属（MIM）电容器。有源芯片面积为160µm×200µm。在2.4 GHz时，在电源电压为1v、功耗仅为3.2 mW的情况下，测量到的单边带（SSB）噪声系数为13.9 dB，电压增益为11.9 dB， IIP3为-3 dBm。在电源电压为1.8 V时，功耗为8.1 mW， SSB噪声系数为12.9 dB，电压增益为16 dB， IIP3为1 dBm
Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-µm CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 µm×200 µm. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW