A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-$\mu{\hbox {m}}$ CMOS Technology
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-$\mu{\hbox {m}}$ CMOS Technology
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DOI:
10.1109/jssc.2011.2116430
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发表时间:
2011-03
影响因子:
5.4
通讯作者:
Shih-Hao Huang;Wei-Zen Chen;Yu-Wei Chang;Yang-Tung Huang
中科院分区:
文献类型:
--
作者:
Shih-Hao Huang;Wei-Zen Chen;Yu-Wei Chang;Yang-Tung Huang
This paper describes the design of a 10-Gb/s fully integrated CMOS optical receiver, which consists of a novel spatially-modulated photo detector (SMPD), a low-noise trans-impedance amplifier (TIA), and a post-limiting amplifier on a single chip. The bandwidth of proposed meshed SMPD can be boosted up to 6.9 GHz under a reverse-biased voltage of 14.2 V. The measured responsivity of the meshed SMPD is 29 mA/W as illuminated by 850-nm light source. To compensate the relatively low responsivity of on-chip CMOS photo detector (PD), a high-gain TIA with nested feedback and shunt peaking is proposed to achieve low-noise operation. The optical receiver is capable of delivering 25-kΩ conversion gain when driving 50-Ω output loads. For a PRBS test pattern of 27- 1, the 10-Gb/s optoelectronic integrated circuit (OEIC) has optical sensitivity of - 6 dBm at a bit-error rate (BER) of 10 -11. Implemented in a generic 0.18-μm CMOS technology, the chip area is 0.95 mm by 0.8 mm. The trans-impedance amplifier, post amplifier, and output buffer respectively drain 38 mW, 80 mW, and 27 mW from the 1.8-V supply.