Microkernel hypervisor for a hybrid ARM-FPGA platform
Microkernel hypervisor for a hybrid ARM-FPGA platform
复制标题
适用于混合 ARM-FPGA 平台的微内核管理程序
DOI：
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发表时间：
2013
期刊：
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通讯作者：
D. Maskell
中科院分区：
文献类型：
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作者：
K. Pham;A. Jain;Jin Cui;Suhaib A. Fahmy;D. Maskell
可重构架构已经在广泛的应用领域中得到了应用，但主要是作为计算密集型功能的静态加速器。由于设计复杂性的挑战，商品计算的采用还没有开始。然而，在严格的时间限制下，可重构架构在不同的孤立任务之间共享硬件方面提供了显著的优势。到目前为止，汽车和航空领域的计算资源合并趋势仅限于非关键系统，因为处理器方法缺乏可预测性和隔离性。混合可重构平台可能提供一个很有前途的解决方案，它允许物理隔离地访问硬件资源，并支持计算要求很高的应用程序，但具有改进的可编程性和管理。我们建议使用在商业混合计算平台（Xilinx Zynq）上运行的基于微内核的管理程序来虚拟化执行和管理软件和硬件任务。我们演示了一个基于CODEZERO管理程序的框架，该管理程序经过修改以利用FPGA结构的功能。它支持离散硬件加速器、动态可重构区域和虚拟结构区域，允许应用程序隔离和更简单地使用硬件资源。一个案例研究演示了多个独立（和隔离）的软件和硬件任务。
Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconfigurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented.