Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity
Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity
复制标题
具有均匀分布开关活动的布局感知转换延迟故障模式生成
DOI：
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发表时间：
2008
影响因子：
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通讯作者：
M. Tehranipoor
中科院分区：
文献类型：
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作者：
Jeremy Lee;M. Tehranipoor
随着芯片集成度的不断提高以及技术扩展迫使工作电压不断降低，现代设计已变得更容易受到电源电压噪声的影响。然而，即使具有良好设计的配电网络，现代全速测试模式生成技术也不考虑网络将能够提供的最大电流吞吐量。结果，常规的转换延迟故障模式生成倾向于创建导致高于平均值的功能切换的多个模式，这可能导致测试期间的定时和/或功能故障。在本文中，我们提出了一个流程，它结合了布局信息和局部的切换活动，在模式生成过程中提供洞察量的可容忍的切换。这将防止IR压降相关的热点和芯片的利用不足，因为切换活动可以均匀地分布在整个设计中。本文中给出的结果表明，与我们以前的流程相比，我们有了显着的改进，而不会对故障覆盖率和模式计数产生负面影响。
As chip integration continues to increase and technology scaling is forcing the operating voltage to decrease, modern designs have become more susceptible to supply voltage noise. However, even with a well designed power distribution network, modern at-speed test pattern generation techniques do not consider the maximum current throughput the network will be able to provide. As a result, conventional transition delay fault pattern generation tends to create a number of patterns that cause higher-than-average functional switching, which may cause timing and/or functional failures during test. In this paper, we propose a flow that incorporates the layout information and the locality of the switching activity during pattern generation to provide insight into the amount of tolerable switching. This will prevent both IR-drop related hot-spots and under-utilization of the chip since the switching activity can be evenly spread across the design. The results presented in this paper show significant improvement over our previous flow without negatively impacting fault coverage and pattern count.