High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder
High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder
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DOI：
10.1109/icecs.2010.5724533
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
V. S. Rosa;L. M. Silva;S. Bampi
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文献类型：
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作者：
V. S. Rosa;L. M. Silva;S. Bampi
提出了一种用于H.264/AVC CABAC熵编码的算术编码器的硬件设计方案。提出了三种不同的体系结构，能够达到高清晰度编码水平，每个时钟周期的仓位处理速率从0.63到1个仓位。ASIC和现场可编程门阵列的综合结果表明，它们都能够达到H.264视频编码标准5级(非常高清晰度)所要求的码率。结果表明，最大效率为167kBins/Gate.s和105GBins/J。
This paper presents a hardware proposal of an arithmetic encoder for the H.264/AVC CABAC entropy encoder. Three different architectures are presented capable of reaching high definition encoding levels with bin processing rates ranging from 0.63 to 1 bins per clock cycle. ASIC and FPGA synthesis results from the proposed architectures show that all of them are able to reach the required bitrate for the Level 5 (very high definition) of the H.264 video encoding standard. These results present a maximum efficiency of 167 kBins/Gate.s and 105 GBins/J.