Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering
复制标题
伽罗瓦域算术电路的形式分析-并行验证与逆向工程
DOI:
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发表时间:
2018
影响因子:
2.9
通讯作者:
M. Ciesielski
中科院分区:
文献类型:
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作者:
Cunxi Yu;M. Ciesielski
Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial <inline-formula> <tex-math notation="LaTeX">${P(x)}$ </tex-math></inline-formula>, which affects final hardware implementation. This paper presents a computer algebra technique that performs verification and reverse engineering of GF(<inline-formula> <tex-math notation="LaTeX">${2^{m}}$ </tex-math></inline-formula>) multipliers directly from the gate-level implementation. The approach is based on extracting a unique irreducible polynomial in a parallel fashion and proceeds in three steps: 1) determine the bit position of the output bits; 2) determine the bit position of the input bits; and 3) extract the irreducible polynomial used in the design. We demonstrate that this method is able to reverse engineer GF(<inline-formula> <tex-math notation="LaTeX">${2^{m}}$ </tex-math></inline-formula>) multipliers in <inline-formula> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> threads. Experiments performed on synthesized <italic>Mastrovito</italic> and <italic>Montgomery</italic> multipliers with different <inline-formula> <tex-math notation="LaTeX">${P(x)}$ </tex-math></inline-formula>, including NIST-recommended polynomials, demonstrate high efficiency of the proposed method.