System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
复制标题
高能效 3D 堆叠宽 I/O DRAM 的系统和电路级功耗建模
DOI：
10.7873/date.2013.061
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
K. Goossens
中科院分区：
文献类型：
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作者：
K. Chandrasekar;C. Weis;B. Akesson;N. Wehn;K. Goossens
JEDEC最近推出了3D堆叠宽I/O DRAM存储器的新标准，该标准定义了它们的架构，设计，功能和时序行为。宽I/O DRAM与前一代DRAM相比具有改进的性能/功率权衡，提供了下一代嵌入式和高性能计算系统所需的极其节能的绿色存储器解决方案。随着工业界和学术界都在推动评估和使用这些备受期待的存储器，迫切需要针对宽I/O DRAM的精确功耗模型，以实现DRAM堆叠SoC架构中的高效集成和能源管理。在本文中，我们提出了第一个系统级功耗模型的3D堆叠宽I/O DRAM存储器，几乎是准确的详细电路级功耗模型的3D-DRAM。为了验证其准确性，我们通过实验将其针对不同内存工作负载和操作的功率和能量估计与电路级3D-DRAM功率模型的功率和能量估计进行比较，并显示两组估计之间的差异小于2%。
JEDEC recently introduced its new standard for 3D-stacked Wide I/O DRAM memories, which defines their architecture, design, features and timing behavior. With improved performance/power trade-offs over previous generation DRAMs, Wide I/O DRAMs provide an extremely energy-efficient green memory solution required for next-generation embedded and high-performance computing systems. With both industry and academia pushing to evaluate and employ these highly anticipated memories, there is an urgent need for an accurate power model targeting Wide I/O DRAMs that enables their efficient integration and energy management in DRAM stacked SoC architectures. In this paper, we present the first system-level power model of 3D-stacked Wide I/O DRAM memories that is almost as accurate as detailed circuit-level power models of 3D-DRAMs. To verify its accuracy, we experimentally compare its power and energy estimates for different memory workloads and operations against those of a circuit-level 3D-DRAM power model and show less than 2% difference between the two sets of estimates.