Pinch-off Voltage Lowering in Polycrystalline-Silicon Thin-Film Transistors
Pinch-off Voltage Lowering in Polycrystalline-Silicon Thin-Film Transistors
复制标题
多晶硅薄膜晶体管的夹断电压降低
DOI：
10.1143/jjap.50.014301
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
H. Ikeda and N. Sano
中科院分区：
文献类型：
--
作者：
Yuichiro Yamaguchi;Masatsugu Shouji;and Yoshiyuki Suda;宮本明;Yasuhiko Ishikawa and Kazumi Wada;H. Ikeda and N. Sano
报道了多晶硅薄膜晶体管（poly-SiTFT）输出特性中的夹断电压（Vp）降低现象，并通过测量和器件模拟进行了研究。随着陷阱密度的增加，观察到的Vp变得小于理想的Vp，同时保持与栅源电压（Vgs）的线性关系。器件模拟分析揭示了Vp降低的两种机制。一个是由于起始栅漏电压（V gd）的增加而导致的电流饱和，导致漏极区变得高阻，这源于表面电势随着Vgs逐渐增加。这被解释为传统夹断概念的扩展。另一个是电流限制，由晶界（GB）和在漏极边缘，这是特有的多晶硅TFT的晶粒内电导控制。在此基础上，提出了一个GB电导限制的载流子输运模型。它与测量的良好协议表明，该模型用于描述Vp降低的适用性。
Pinch-off voltage (V p) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed V p becomes smaller than the ideal V p while maintaining a linear relationship with the gate–source voltage (V gs). The device simulation analysis revealed two mechanisms for V p lowering. One is current saturation due to the increase in onset gate–drain voltage (V gd), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with V gs. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing V p lowering.