De-blocking Filter Design for HEVC and H.264/AVC
De-blocking Filter Design for HEVC and H.264/AVC
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DOI：
10.1007/978-3-642-34778-8_25
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发表时间：
2012-12
期刊：
影响因子：
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通讯作者：
Muchen Li;Jinjia Zhou;Dajiang Zhou;Xiao Peng;S. Goto
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文献类型：
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作者：
Muchen Li;Jinjia Zhou;Dajiang Zhou;Xiao Peng;S. Goto
As the successor of H.264/AVC, HEVC inherits the basic property of H.264/AVC and gives some new features. This paper introduces a novel dual-standard de-blocking filter architecture which could support both of the HEVC and H.264/AVC standards. It takes 48 clock cycles for H.264/AVC and 24 cycles for HEVC for every 16×16 block. The proposed unified-cross based processing order greatly reduces the design complexity. The proposed architecture occupies 43.3k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of quad-full high definition (QFHD) on 60fps for H.264/AVC and super hi-vision (SHV) on 60fps for HEVC. In addition, the total power consumption could be reduced by 37.8% in skipping mode when the edges need not be filtered.
