Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
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变化训练的休眠缓存（VTD-Cache）：用于细粒度电压缩放的历史训练变化感知休眠缓存
DOI：
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发表时间：
2012
影响因子：
2.8
通讯作者：
F. Kurdahi
中科院分区：
文献类型：
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作者：
Avesta Sasan;K. Amiri;H. Homayoun;A. Eltawil;F. Kurdahi
在本文中，我们介绍“训练有素的淹没缓存”（VTD-CACHE）体系结构。 ，每种缓存方式都可以在不同的电压下采购，其中电压级别的选择取决于以该缓存方式处理变化的内存单元的脆弱性和访问该缓存的可能性是在短暂的训练期之后，拟议的体系结构将微调缓存，从而可以大幅度降低功率，而不是可忽略的遗漏。供应电压设置适应程序的执行模式。在一个案例研究中，在具有较小面积和电源的记忆编译器中，对拟议的32 KB CACHERTUCTERTION的SimpleScalar模拟报告了超过57％的功耗超过57％执行时间罚款小于1％。
In this paper we present the “Variation Trained Drowsy Cache” (VTD-Cache) architecture. VTD-Cache allows for a significant reduction in power consumption while addressing reliability issues raised by memory cell process variability. By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and the likelihood of access to that cache location. After a short training period, the proposed architecture will micro-tune the cache, allowing significant power reduction with negligible increase in the number of misses. In addition, the proposed architecture actively monitors the access pattern and reconfigures the supply voltage setting to adapt to the execution pattern of the program. The novel and modular architecture of the VTD-Cache and its associated controller makes it easy to be implemented in memory compilers with a small area and power overhead. In a case study, the SimpleScalar simulation of the proposed 32 kB cache architecture reports over 57% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead of less than 4% and an execution time penalty smaller than 1%.