Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU
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DOI：
10.1109/vlsic.2014.6858403
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发表时间：
2014-06
期刊：
2014 Symposium on VLSI Circuits Digest of Technical Papers
影响因子：
--
通讯作者：
H. Noguchi;K. Ikegami;N. Shimomura;T. Tanamoto;J. Ito;S. Fujita
H. Noguchi;K. Ikegami;N. Shimomura;T. Tanamoto;J. Ito;S. Fujita
中科院分区：
其他
文献类型：
--
作者：
H. Noguchi;K. Ikegami;N. Shimomura;T. Tanamoto;J. Ito;S. Fujita

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本文提出了一种基于高级垂直STT-MRAM的新型非挥发级缓存（LLC），以减少LLC的总功耗。提出的有限责任公司具有双感应救赎方案的新读数电路，该方案增强了STT-MRAM以及典型的错误校正代码（ECC）的可靠性。每功率CPU性能与基于SRAM的嵌入式DRAM和常规STT-MRAM LLC的比较表明，提出的新型非挥发性LLC最适合大型LLC。
This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.