PURR: a primitive for reconfigurable fast reroute: hope for the best and program for the worst
PURR: a primitive for reconfigurable fast reroute: hope for the best and program for the worst
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DOI：
10.1145/3359989.3365410
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发表时间：
2019-12
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通讯作者：
Marco Chiesa;R. Sedar;G. Antichi;Michael Borokhovich;Andrzej Kamisiński;G. Nikolaidis;S. Schmid
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作者：
Marco Chiesa;R. Sedar;G. Antichi;Michael Borokhovich;Andrzej Kamisiński;G. Nikolaidis;S. Schmid
高度依赖的通信网络通常依靠某种快速的重新透露（FRR）机制，该机制允许在数据平面上快速重新布置流量贡献是可编程数据平面的FRR原始性，即通过避免purr purr purre，它可以提供低故障延迟和高开关吞吐量多次发生故障，并带有最小的记忆要求，通过与经典的“弦理论”（即语言学）建立了有趣的连接，从而确保了紧凑的转发表，尤其是最短的常见超级式问题。快速匹配项转发体系结构（例如，PISA），并支持任意网络范围的FRR机制的实现。证明Purr在实施最新的FRR机制时，将TCAM存储器的占用率提高了1.5倍-10.8倍。与基于循环数据包的方法相比，X - 5.5倍和1.2x - 2x分别是相比。
Highly dependable communication networks usually rely on some kind of Fast Re-Route (FRR) mechanism which allows to quickly re-route traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation. PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic "string theory" (i.e., stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures (e.g., PISA) and supports the implementation of arbitrary network-wide FRR mechanisms. Our simulations and prototype implementation (on an FPGA and Tofino) show that PURR improves TCAM memory occupancy by a factor of 1.5x--10.8x compared to a naïve encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of 2.8x--5.5x and 1.2x--2x, respectively, compared to approaches based on recirculating packets.