Applying speculation techniques to implement functional units
Applying speculation techniques to implement functional units
复制标题
应用推测技术来实现功能单元
DOI：
--
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
F. Tirado
中科院分区：
文献类型：
--
作者：
Alberto A. Del Barrio;M. Molina;J. Mendias;Esther Andres Perez;R. Hermida;F. Tirado
本文证明了利用进位的估计和预测来提高由满加法器复制构建的功能单元的性能，同时保持低面积惩罚。加法器和乘法器是这组功能单元中最具代表性的模块。使用这些设计技术，模块的性能提升幅度在20%到50%之间，而面积开销仅为5%左右。这些功能单元适用于异步电路，但它们也可以通过推测技术引入同步电路。其基本思想在于估计功能单元的某些部分的执行情况，允许每个部分独立并行地操作。这些模块被连接起来建造更大的模块。模拟结果表明，对于某些应用程序，可以做出比基于位的估计更准确的预测。预测还有一个优点，它们可以被引入乘数设计中，而估计器则不能。这些预测类似于处理器中的分支预测中使用的预测。
This paper justifies the use of estimation and prediction of carries to increase the performance of functional units built with the replication of full adders while keeping a low area penalization. Adders and multipliers are the most representative modules in this group of functional units. The use of these design techniques allows the implementation of modules with performance improvements ranging from 20% to 50% with only an area overheads around 5%. These functional units are suitable for asynchronous circuits but they could also be introduced in synchronous circuits with speculative techniques. The basic idea consists in estimating the carry out from some parts of the functional units, allowing every part to operate independently and in parallel. These modules are connected to build bigger ones. Results from simulations show that for some applications it is possible to make predictions even more accurate that the bit-based estimation. Predictions have also the advantage they can be introduced in the multipliers design, whether estimators cannot. These predictions are similar to the ones used in the branch prediction in a processor.