Cache Partitioning Strategies for 3-D Stacked Vector Processors
Cache Partitioning Strategies for 3-D Stacked Vector Processors
复制标题
3-D 堆叠式矢量处理器的缓存分区策略
DOI：
10.1109/3dic.2010.5751453
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Hiroaki Kobayashi
中科院分区：
文献类型：
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作者：
Yusuke Funaya;Ryusuke Egawa;Hiroyuki Takizawa;Hiroaki Kobayashi
一种用于向量处理器的片上高速缓冲存储器，称为向量高速缓存，已经被提出来实现高持续的存储器带宽，这与未来向量处理器的高计算性能相平衡。在我们之前的研究中，从架构设计的角度来看，它清楚地表明，3D芯片堆叠技术可以增加向量缓存的容量，从而提高向量处理器的性能。然而，三维芯片堆叠技术的矢量高速缓存的详细设计还没有得到很好的讨论。因此，目前还不清楚矢量缓存在成本、延迟和能耗方面能从3D芯片堆叠技术中获益多少。在本文中，矢量缓存的详细设计，以发挥三维芯片堆叠技术的优势，如减少长导线和能源消耗。在该高速缓存的设计中，本文研究了两种策略，将矢量缓存划分为若干块，并将它们放置在多个层上。一种高速缓存分区策略更加强调减少长线的数量。另一种策略减少了硅通孔（TSV）的数量。本文评估延迟，能耗，和TSV的数量在每个缓存分区策略中使用。本文还讨论了适用于矢量处理器的3D缓存配置。
An on-chip cache memory for vector processors, named vector cache, has been proposed to realize a high sustained memory bandwidth, which is balanced with the high computational performance of future vector processors. In our previous research, from the viewpoint of architectural design, it is clearly shown that the 3D die-stacking technology can increase the capacity of the vector cache and thereby the performance of vector processors. However, detailed design of vector caches with the 3D die-stacking technology has not been discussed well yet. Therefore it is still unclear how much the vector cache can benefit from the 3D die-stacking technology in terms of cost, latency, and energy consumption. In this paper, the vector caches are designed in detail so as to exploit the advantages of the 3D die-stacking technologies, such as reductions in long wires and energy consumption. In the cache design, this paper examines two strategies to partition the vector caches into some blocks and to place them onto multiple layers. One cache partitioning strategy places more emphasis on the reduction in the number of long wires. The other strategy reduces the number of through-silicon vias (TSVs). This paper evaluates latency, energy consumption, and the number of TSVs used in each cache partitioning strategy. This paper also discusses the 3D cache configuration suitable for vector processors.