Computing in Memory With Spin-Transfer Torque Magnetic RAM
Computing in Memory With Spin-Transfer Torque Magnetic RAM
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DOI：
10.1109/tvlsi.2017.2776954
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发表时间：
2018-03-01
影响因子：
2.8
通讯作者：
Raghunathan, Anand
中科院分区：
文献类型：
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作者：
Jain, Shubham;Ranjan, Ashish;Raghunathan, Anand
内存计算是解决计算系统中处理器-内存数据传输瓶颈的一种有前途的方法。我们提出了自旋转移矩计算存储器（STT-CiM），一个设计的存储器计算与自旋转移矩磁性RAM（STT-MRAM）。自旋电子存储器的独特性质允许同时启用阵列内的多个字线，从而打开了使用单个访问直接感测存储在多个行中的值的功能的可能性。我们建议修改STT-MRAM外围电路，利用这一原则来执行逻辑，算术和复杂的向量运算。我们解决的挑战，可靠的内存中的计算过程中的变化，通过扩展纠错码方案，以检测和纠正错误，发生在CiM操作。我们还解决了如何STT-CiM应该被集成在一个通用的计算系统的问题。为此，我们提出了架构增强处理器指令集和片上总线，使STT-CiM被用作暂存器存储器。最后，我们提出了数据映射技术，以提高STT-CiM的有效性。我们评估STT-CiM使用设备到架构建模框架，并集成周期精确模型的STT-CiM与商业处理器和片上总线（Nios II和Avalon从英特尔）。我们的系统级评估表明，STT-CiM提供了系统级的性能平均提高了3.93倍（高达10.4倍），并同时降低了存储系统的能量平均3.83倍（高达12.4倍）。
In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose spin-transfer torque compute-in-memory (STT-CiM), a design for in-memory computing with spin-transfer torque magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending error-correction code schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a general-purpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiMusing a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides the system-level performance improvements of 3.93 times on average (up to 10.4 times), and concurrently reduces memory system energy by 3.83 times on average (up to 12.4 times).