Implications of clock distribution faults and issues with screening them during manufacturing testing
Implications of clock distribution faults and issues with screening them during manufacturing testing
复制标题
时钟分配故障的影响以及在制造测试期间对其进行筛选的问题
DOI：
10.1109/tc.2004.1275295
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发表时间：
2004
影响因子：
3.7
通讯作者：
T. M. Mak
中科院分区：
文献类型：
--
作者：
C. Metra;Stefano Di Francescantonio;T. M. Mak
基于参考微处理器的真实的工艺数据，导出了最可能影响时钟分配网络信号的制造缺陷的故障模型。它们的概率是通过在参考微处理器的实际布局上执行的感应故障分析来估计的。最有可能的故障的影响进行了评估的电气电平模拟。我们发现，与常见的假设相反，只有一小部分这样的故障导致灾难性的故障，在制造测试过程中很容易检测到。相反，大多数这样的故障导致在制造测试期间不太可能被检测到的局部故障，尽管它们可能损害微处理器操作和可靠性。特别是，我们发现，在制造测试过程中，只有12%的情况下可以检测到时钟故障。更令人惊讶的是，我们还发现，在10%的情况下，未检测到的时钟故障也使测试过程本身无效。
Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself.