High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing
复制标题
DOI：
10.1109/jssc.2020.3021066
复制
发表时间：
2021-02-01
影响因子：
5.4
通讯作者：
Gu, Jie
中科院分区：
文献类型：
--
作者：
Chen, Zhengyu;Gu, Jie
时间序列分类（TSC）是机器学习中的一个挑战性问题，并为提高其速度和计算效率而做出了重大努力。在各种方法中，动态时间扭曲（DTW）算法是TSC最普遍的方法之一，由于其简洁性和一般性。为了改善操作的吞吐量，这项工作提出了使用混合信号时域（TD）计算的混合信号DTW加速器，其中使用时间脉冲编码和处理信号。通过专门设计的时间触发器（TFF）电路启用了管道操作，从而导致操作的性能和可扩展性的显着提高。实施和测量了65 nm的CMOS测试芯片。与TSC上的先前工作相比，结果显示吞吐量的9倍以上。由于大多数现有的TD设计都缺乏TD存储元素，因此这项工作利用TD计算中的顺序电路元素扩展了基于时间电路的能力。
Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than 9x improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.