An approach for implementing efficient superscalar CISC processors
An approach for implementing efficient superscalar CISC processors
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一种实现高效超标量 CISC 处理器的方法
DOI：
10.1109/hpca.2006.1598111
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
James E. Smith
中科院分区：
文献类型：
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作者：
Shiliang Hu;I. Kim;Mikko H. Lipasti;James E. Smith
提出和分析了一个集成的硬件/软件共同设计的CISC处理器。目标是高性能和降低的复杂性。尽管X86 ISA是针对的，但总体方法适用于其他CISC ISA。为了在经常执行的代码序列上提供高性能，完全透明的动态翻译软件将CISC超块分解为RISC风格的Micro-ops。然后，对成对的依赖微型ops进行重新排序，并将其融合到以大型隐藏的代码缓存中固定的宏观上。从代码缓存中获取宏观操作，并在整个管道中处理为单个单元。因此，减少了指令级别的通信和管理，并且更好地利用了问题缓冲区和注册文件端口等处理器资源。此外，融合的说明自然导致了管道指令计划（问题）逻辑，并可以使用3-1 alus倒塌，从而导致了许多简化的结果转发逻辑。评估了SPEC2000基准的稳态性能，并显示出类似于两个宽度超大量表处理器的复杂性的拟议的X86实现，可提供与常规四宽SupersCalar处理器相当的性能（每个周期指令）。
An integrated, hardware/software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targeted, the overall approach is applicable to other CISC ISAs. To provide high performance on frequently executed code sequences, fully transparent dynamic translation software decomposes CISC superblocks into RISC-style micro-ops. Then, pairs of dependent micro-ops are reordered and fused into macro-ops held in a large, concealed code cache. The macro-ops are fetched from the code cache and processed throughout the pipeline as single units. Consequently, instruction level communication and management are reduced, and processor resources such as the issue buffer and register file ports are better utilized. Moreover, fused instructions lead naturally to pipelined instruction scheduling (issue) logic, and collapsed 3-1 ALUs can be used, resulting in much simplified result forwarding logic. Steady state performance is evaluated for the SPEC2000 benchmarks, and a proposed x86 implementation with complexity similar to a two-wide superscalar processor is shown to provide performance (instructions per cycle) that is equivalent to a conventional four-wide superscalar processor.