Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories with PIETT
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories with PIETT
复制标题
利用 PIETT 实现域壁存储器的全面移位容错
DOI：
10.1109/tc.2022.3188206
复制
发表时间：
2022
影响因子：
3.7
通讯作者：
Jones, Alex K.
中科院分区：
文献类型：
--
作者：
Ollivier, Sebastien;Longofono, Stephen;Dutta, Prayash;Hu, Jingtong;Bhanja, Sanjukta;Jones, Alex K.
自旋畴壁存储器（DWM）提供了改进的存储密度和能量相比，传统的存储器，但易受移位故障。我们提出了PIETT（Pinning，Insertion，Erasure，andTranslation-faultTolerance）改进的错位校正与现有技术相比。PIETT提出了一种派生的错误校正与多域访问方法相结合，以检测和校正任意移位距离后的至少三个错位故障。此外，未对准和钉扎故障率的特点是在DWM纳米线，表明钉扎故障是一个重要的关注DWM。因此，PIETT是第一种结合联合收割机校正随机存取DWM中的未对准和钉扎故障的方法。它还介绍了新的PIETT横向接入点（TAP），它利用一种新的写访问模式，可以设置/重置多个域在一个单一的内在操作，并可以存储移位距离检测代码。通过允许在固有移位距离的移位之间进行检查（例如，3个域），每个纳米线使用单个TAP扩展了未对准保护，并确定所需的校正偏移以校正所有纳米线中的故障。两个TAP扩展了错位保护，以纠正多个位置的错位，并通过检测纳米线每个末端的不同位移距离来检测钉扎。PIETT利用钉扎纳米线位置的知识来引导具有存储在附加奇偶校验纳米线中的一个附加奇偶校验位的修改的SECDED ECC。因此，TAP模式中的PIETT可以使用清理来校正无限的、潜在的多位置的未对准故障以及多达三个钉扎故障或多达两个钉扎故障和多达一个位翻转故障。与现有技术的DWM未对准校正相比，PIETT在平均故障时间方面提供了8到21个数量级的改进，具有类似或更好的面积开销，并且仅1%的系统性能下降。
Spintronic domain-wall memories (DWMs) offer improved memory density and energy compared to conventional memories, but are susceptible to shifting faults. We propose PIETT (Pinning,Insertion,Erasure, andTranslation-faultTolerance) for improved misalignment correction versus the state of the art. PIETT proposes a derived error correction combined with multi-domain access approach to detect and correct a minimum of three misalignment faults after an arbitrary shift distance. Moreover, the rate of both misalignment and pinning faults are characterized in DWM nanowires, demonstrating that pinning faults are a significant concern to DWM. As such, PIETT is the first method to combine correction of misalignment and pinning faults in random access DWMs. It also introduces novel PIETT Transverse Access Points (TAPs), which utilize a novel write access mode that can set/reset multiple domains in a single intrinsic operation and can store shift distance detection codes. By allowing checks between shifts of the intrinsic shift distance (e.g., 3 domains), using a single TAP per nanowire expands misalignment protection and determines the needed corrective shifts to correct faults in all nanowires. Two TAPs expands misalignment protection to correct misalignment by more than one position and detects pinning by detecting different shift distances at each extremity of the nanowire. PIETT leverages knowledge of pinned nanowire locations to guide a modified SECDED ECC with one additional parity bit stored in additional parity nanowires. Thus, PIETT in TAP mode can correct unlimited, potentially multi-position, misalignment faults and either up to three pinning faults or up to two pinning faults with up to one bit flip fault using scrubbing. PIETT provides 8 to 21 orders of magnitude improvement in mean-time-to-failure with similar or better area overhead and only a 1% system performance degradation compared to state of the art DWM misalignment correction.