DC‐20 GHz 5‐BIT CMOS digital step attenuator with low insertion loss and phase error
DC‐20 GHz 5‐BIT CMOS digital step attenuator with low insertion loss and phase error
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DOI：
10.1002/mop.27448
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发表时间：
2013-04
影响因子：
1.5
通讯作者：
Moon-Kyu Cho;Donghyun Baek;Jeong‐Geun Kim
中科院分区：
文献类型：
--
作者：
Moon-Kyu Cho;Donghyun Baek;Jeong‐Geun Kim
本文提出了一种采用标准 0.13 μm CMOS 工艺的相控阵天线，具有低插入损耗和相位误差的 5 位宽带数字步进衰减器。在 DC-20 GHz 下，可实现 31 dB 的最大衰减，LSB 为 1 dB。 DC-20 GHz 时，测量的参考状态插入损耗 <11 dB，输入和输出回波损耗 <−10 dB。均方根 (RMS) 相位和幅度误差分别 <2.5° 和 <0.7 dB。使用 1.2 V 电源时电流消耗接近于零。芯片尺寸为 1.04 × 0.48 mm2（包括焊盘）。 © 2012 Wiley periodicals, Inc. Microwave Opt Technol Lett 55:762–764，2013；请访问 wileyonlinelibrary.com 在线查看本文。 DOI：10.1002/mop.27448
This article presents a 5‐bit broadband digital step attenuator with low insertion loss and phase error using a standard 0.13 μm CMOS process for the phased array antenna.The maximum attenuation of 31 dB with the LSB of 1 dB is achieved at DC‐20 GHz. The measured insertion loss of the reference state is <11 dB and the input and output return losses are <−10 dB at DC‐20 GHz. The root mean square (RMS) phase and amplitude errors are <2.5° and <0.7 dB, respectively. The current consumption is near zero with 1.2 V supply. The chip size is 1.04 × 0.48 mm2 including pads. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:762–764, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27448