Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI
Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI
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DOI：
10.1109/ted.2009.2037372
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发表时间：
2010-02
影响因子：
3.1
通讯作者：
X. Luo;Yuangang Wang;Hao Deng;Jie Fan;T. Lei;Yong Liu
中科院分区：
文献类型：
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作者：
X. Luo;Yuangang Wang;Hao Deng;Jie Fan;T. Lei;Yong Liu
提出了一种在部分绝缘体上硅（PSOI）上埋置低k介质的高压横向双扩散金属氧化物半导体晶体管（LK PSOI）。低k值增强了电介质（EI）中的电场强度。硅窗口不仅使衬底分担击穿电压，调制SOI层中的电场分布，而且消除了自加热效应。与常规PSOI相比，kI = 2的LK PSOI的EI和BV分别提高了74%和19%。
A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-k dielectric (LK PSOI) is proposed. The low-k value enhances the electric field strength in the dielectric (EI). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the EI and BV of LK PSOI with kI = 2 are enhanced by 74% and 19%, respectively.