Effect of CNTFET Parameters on Novel High Stable and Low Power: 8T CNTFET SRAM Cell
Effect of CNTFET Parameters on Novel High Stable and Low Power: 8T CNTFET SRAM Cell
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CNTFET 参数对新型高稳定低功耗的影响：8T CNTFET SRAM 单元
DOI：
10.1007/s42341-021-00346-9
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发表时间：
2021
影响因子：
1.9
通讯作者：
K. Gunavathi
中科院分区：
文献类型：
--
作者：
M. Elangovan;K. Gunavathi
在本文中，我们研究了基于8晶体管（8 T）碳纳米管场效应晶体管（CNTFET）的静态随机存取存储器（SRAM）电池的稳定性和功耗。在写、保持和读操作中，观察了所提出的8 T CNTFET SRAM单元的功率和噪声性能。并与传统的6 T和8 T CNTFET SRAM电池进行了功耗和噪声裕度的比较。从仿真结果可以看出，在写入、保持和读取操作期间，所提出的结构比传统的CNTFET SRAM单元消耗更少的功率。通过计算静态噪声裕度（SNM）来测量，所提出的8 T CNTFET SRAM单元比传统CNTFET SRAM单元具有更高的写入和保持模式稳定性。CNTFET的性能取决于几个参数，如介电常数（Kox），氧化物厚度（Hox），电源电压，节距值和温度。观察了这些参数对传统和新型CNTFET SRAM电池功率和稳定性的影响。值得注意的是，所提出的8 T CNTFET SRAM电池在PVT变化期间具有良好的稳定性，并且比传统的6 T和8 T CNTFET SRAM电池消耗更少的功率。在布局前和布局后的模拟中观察了所提出的8 T CNTFET SRAM的性能指标。所有仿真均采用斯坦福大学32nm CNTFET模型和HSPICE仿真工具进行。
In this paper, we have investigated the stability and power consumption of an 8 transistor (8 T) carbon nanotube field-effect transistor (CNTFET) based static random-access memory (SRAM) cell. The power and noise performances of the proposed 8 T CNTFET SRAM cell are observed for write, hold and read operations. The power consumption and noise margin of the proposed 8 T CNTFET SRAM cell are compared with that of conventional 6 T and 8 T CNTFET SRAM cells. From the simulation results, it is noted that during the write, hold, and read operations, the proposed structure consumes less power than the conventional CNTFET SRAM cells. The proposed 8 T CNTFET SRAM cell provides greater write and hold modes stability than conventional CNTFET SRAM cells, which is measured by calculating static noise margin (SNM). The performance of CNTFET depends on several parameters like dielectric constant (Kox), oxide thickness (Hox), supply voltage, pitch value, and temperature. The effect of these parameters on the power and stability of the conventional and proposed CNTFET SRAM cells are observed. It is noted that the proposed 8 T CNTFET SRAM cell provides good stability during PVT variation and consumes less power than conventional 6 T and 8 T CNTFET SRAM cells. The performance metrics of the proposed 8 T CNTFET SRAM are observed for both pre-layout and post-layout simulations. All the simulations are performed using the Stanford University 32 nm CNTFET model with the HSPICE simulation tool.