Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
复制标题
DOI：
10.1109/isca45697.2020.00051
复制
发表时间：
2020-04
期刊：
影响因子：
--
通讯作者：
Prakash Murali;D. Debroy;K. Brown;M. Martonosi
中科院分区：
文献类型：
--
作者：
Prakash Murali;D. Debroy;K. Brown;M. Martonosi
被困的离子（TI）是建立嘈杂的中间量子量子（NISQ）硬件的领先候选人。在大小上，具有5-20个Quarbits，通常使用具有基本可扩展性限制的单个陷阱体系结构。在基于QCCD的Ti设备中，提出了50-100量子器TI设备的里程碑，称为量子电荷耦合设备（QCCD）。被证明，建立50-100量子系统的系统具有挑战性需要符合潜水员的应用资源需求。在实现50-100配额的基于QCCD的TI系统中，我们进行了广泛的应用程序驱动的建筑研究，评估了陷阱尺寸，通信拓扑和操作实施方法的关键设计选择。 ，我们建立了一个设计工具流，该工具流将QCCD体系结构的参数作为输入，以及一组应用程序和现实的硬件性能模型工具流将应用程序映射到目标设备上，并使用六个应用程序和几个硬件设计点模拟其执行方式，例如运行时间，可靠性和设备噪声率。最多三个数量级。调整这些选择，以实现高度可靠和性能的应用程序，并通过行业和学术上的努力来建立50-100 QUBITS的TI设备，我们的见解有可能影响QC硬件的近距离设备系统。
Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture’s parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.